1. Field of the Invention
The present invention relates to a microcomputer with a transmission/reception buffer in which a data transmission to a host computer and a data reception from the host computer are performed, and more particularly to a microcomputer in which various problems occurring in a data exchange with the host computer are solved.
2. Description of Related Art
FIG. 12 is a block diagram showing the configuration of a conventional system composed of a conventional microcomputer and a host computer connected with the conventional microcomputer. In FIG. 12, a reference sign 25 indicates a microcomputer, a reference sign 26 indicates a host computer, a reference sign 27 indicates a central processing unit, a reference sign 28 indicates a read only memory (ROM), a reference sign 29 indicates a random access memory (RAM), a reference sign 30 indicates an enciphering circuit for performing a data enciphering processing and a data deciphering processing, a reference sign 31 indicates an integrated circuit (IC) card interface circuit for exchanging data with an IC card, a reference sign 32 indicates a re-writable ROM for storing various types of data, a reference sign 33 indicates a direct memory access controller (DMAC), a reference sign 34 indicates a host interface circuit for receiving and transmitting data from/to the host computer 26, and a reference sign 35 indicates an internal data bus having an 8-bit bus width. In this prior art, as information received and transmitted between the host computer 26 and the host interface circuit 34, data passing through an external data bus having an 8-bit bus width, a pair of an external read control signal and an external write signal (R/W), an external chip selection (CS) signal and other various control signals are shown in FIG. 12.
FIG. 13 is a block diagram showing the configuration of the host interface circuit 34 of the conventional microcomputer and a periphery of the host interface circuit 34. In FIG. 13, a reference sign 36 indicates a transmission/reception buffer arranged between the external data bus and the internal data bus 35, a reference sign 37 indicates a reception flag, a reference sign 38 indicates a transmission flag for outputting a read-out signal, and a reference sign 39 indicates a ready flag for outputting a busy signal.
Next, an operation will be described.
FIG. 14 is a flow chart showing the procedure performed in the conventional system shown in FIG. 12 and FIG. 13 according to a program executed in the central processing unit 27 in cases where data is written in the transmission/reception buffer 36. In FIG. 14, in a data transmission from the host computer 26 to the microcomputer 25 functioning as a slave processor, an operation of the host interface circuit 34 is started to prepare the holding of the reception data in the transmission/reception buffer 36. Thereafter, in a step ST15, it is judged by referring to a value of the reception flag 37 whether or not reception data not yet read-out exists in the transmission/reception buffer 36. In cases where reception data not yet read-out exists, in a step ST16, the central processing unit 27 accesses to the transmission/reception buffer 36 to read out the reception data not yet read-out. Thereafter, in a step ST17, it is judged by referring to a value of the reception flag 37 whether or not next reception data is received in the transmission/reception buffer 36. In cases where next reception data is received from the host computer 26, the procedure returns to the step ST15. In contrast, in cases where next reception data is not received, the procedure is completed.
FIG. 15 is a flow chart showing the procedure performed in the conventional system shown in FIG. 12 and FIG. 13 according to a program executed in the central processing unit 27 in cases where data to be transmitted to the host computer 26 is generated in the central processing unit 27. In FIG. 15, in a data transmission from the microcomputer 25 functioning as a slave processor to the host computer 26, an operation of the host interface circuit 34 is started to prepare the writing of transmission data generated in the central processing unit 27 in the transmission/reception buffer 36. Thereafter, in a step ST18, it is judged by referring to the transmission flag 38 whether or not transmission data to be transmitted to the host computer 26 exists in the transmission/reception buffer 36. In cases where preceding transmission data to be transmitted to the host computer 26 exists in the transmission/reception buffer 36, the procedure waits for the reading-out of the preceding transmission data from the transmission/reception buffer 36. In contrast, in cases where preceding transmission data to be transmitted to the host computer 26 does not exist, in a step ST19, the central processing unit 27 accesses to the transmission/reception buffer 36 to write current transmission data generated in the central processing unit 27 in the transmission/reception buffer 36. Thereafter, it is judged by referring to the transmission flag 38 whether or not next transmission data to be transmitted to the host computer 26 is generated in the central processing unit 27. In cases where next transmission data is generated in the central processing unit 27, the procedure returns to the step ST18. In contrast, in cases where next transmission data is not generated in the central processing unit 27, the procedure is completed.
As is described above, in cases where the data transmission/reception is performed between the host computer 26 and the microcomputer 25, a handshaking described hereinafter in detail is established between the host computer 26 and the microcomputer 25 under the control of the central processing unit 27.
For example, in cases where data is transmitted from the host computer 26 to the microcomputer 25, the host computer 26 sets data on the external data bus, asserts an external chip selection signal set to a low level and drives an external read/write signal to a low level. In response to the signal setting of the host computer 26, in the microcomputer 25, the transmission/reception buffer 36 latches and holds the data transmitted through the external data bus in synchronization with an edge of the external write control signal, a flag is set in the reception flag 37 to inhibit another data holding of the transmission/reception buffer 36. Thereafter, the procedure shown in FIG. 14 is performed according to the flag of the reception flag 37 under the control of the central processing unit 27 to read out the data held in the transmission/reception buffer 36 and to perform the prescribed processing. For example, in cases where enciphered data is received in the microcomputer 25, the enciphered data is transferred from the transmission/reception buffer 36 to an enciphered data buffer of the enciphering circuit 30 to decipher the enciphered data in the enciphering circuit 30, and various operations are performed according to the deciphered data.
Also, in cases where data is transmitted from the microcomputer 25 to the host computer 26, the microcomputer 25 holds the data in the transmission/reception buffer 36. In response to the data holding, a flag is set in each of the transmission flag 38 and the ready flag 39 to inhibit another data holding of the transmission/reception buffer 36. Thereafter, the host computer 26 reads out the data from the transmission/reception buffer 36 according to the states of the transmission flag 38 and the ready flag 39.
After the data read-out, each of the reception flag 37, the transmission flag 38 and the ready flag 39 is reset by a hardware operation of the microcomputer 25 according to an access to the transmission/reception buffer 36 or a data holding state of the transmission/reception buffer 36.
Because the conventional microcomputer 25 has the above-described configuration, in cases where data is exchanged between the upward host computer 26 and the microcomputer 25, various problems described hereinafter occur, so that there is a drawback that an operation reliability in the system using the microcomputer 25 becomes low.
As a first problem, in cases where a flag set in the transmission flag 38 or the reception flag 37 is not reset because an abnormal state occurs in a preceding data transmission/reception, a current data transmission/reception cannot be performed.
As a second problem, in cases where a flag of the ready flag 39 is put down (in other words, a flag indicating a busy state is written in the ready flag 39) because of the occurrence of a certain state during an access operation of the host computer 26 to the microcomputer 25 through the external data bus, the host computer 26 must undesirably wait for a data transmission/reception until the busy flag of the ready flag 39 is put down. Therefore, in the worst case, the whole system including the host computer 26 is undesirably frozen.
As a third problem, because the transmission/reception buffer 36 latches the data transmitted through the external data bus in synchronization with the leading edge of the write control signal in this conventional system, this conventional system cannot be made by using a generally-used host computer in which a data holding time-period (for example, a set-up time or a holding time) is merely prescribed for clocks transmitted through an external system bus. As a result, a specialized high-cost host computer is required as the host computer 26.
As a fourth problem, because the enciphered data received in the transmission/reception buffer 36 is transferred to the buffer of the enciphering circuit 30 and is deciphered, as compared with other data, it takes a long time to convert the enciphered data into a deciphered type usable in the central processing unit 27.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional microcomputer, a microcomputer in which each of the problems occurring in a data exchange with an upward host computer is solved to improve an operation reliability in a system composed of the microcomputer and the host computer.
The object is achieved by the provision of a microcomputer, in which a central processing circuit, storing means, an internal data bus connecting the central processing circuit and the storing means and a transmission/reception buffer arranged between an external data bus and the internal data bus, comprising:
a reception flag which is set according to a write-in to the transmission/reception buffer from an outside and is reset according to a read-out from the transmission/reception buffer to the central processing circuit; and
a transmission flag which is set according to a write-in to the transmission/reception buffer from the central processing circuit and is reset according to a read-out from the transmission/reception buffer to the outside, wherein the central processing circuit accesses to the transmission/reception buffer after the central processing circuit resets the reception flag and the transmission flag.
In the above configuration, in cases where an abnormal state occurs in a preceding data reception in the microcomputer when preceding data is received from the outside such as a host computer, the reception flag is maintained to a set state so as to inhibit a write-in of current data to the transmission/reception buffer in a current data reception. However, because the central processing circuit resets the reception flag before the central processing circuit accesses to the transmission/reception to perform the current data reception, the central processing circuit can receives the current data in the current data reception.
Also, in cases where an abnormal state occurs in a preceding data transmission in the microcomputer when preceding data is transmitted to the outside such as a host computer, the transmission flag is maintained to a set state so as to inhibit a write-in of current data to the transmission/reception buffer in a current data transmission. However, because the central processing circuit resets the transmission flag before the central processing circuit accesses to the transmission/reception to perform the current data transmission, the central processing circuit can write the current data in the current data transmission to read out the current data to the outside. Accordingly, because the central processing circuit can always reset the reception flag even though the reception flag is set and because the central processing circuit can write data in the transmission/reception buffer after the transmission flag is reset regardless of whether the transmission flag is set, even though an abnormal state occurs in the data transmission/reception of the microcomputer not to reset the transmission flag or the reception flag, a next data transmission/reception can be normally performed, so that an operation reliability of the microcomputer can be improved.
It is applicable that the internal data bus and the transmission/reception buffer be formed to correspond to a bus width which is N times (N is a positive integral number) that of the external data bus, and the central processing circuit select either the bus width of the internal data bus or the bus width of the external data bus according to a change-over signal input from the outside to access to the transmission/reception buffer at the selected bus width.
In the prior art, the internal data bus and the transmission/reception buffer are formed to correspond to the same bus width as that of the external data bus. However, in the present invention, because the internal data bus and the transmission/reception buffer are formed to correspond to a bus width which is N times that of the external data bus, a processing time required in the microcomputer can be considerably shortened in the transmission/reception of data having a bit width corresponding to all bus width of the internal data bus and the transmission/reception buffer. In particular, because the used bus width in the accessing of the central processing unit to the transmission/reception buffer is changed over according to the change-over signal input from the outside, the used bus width can be set to a value suitable for a type of data transmitting through the external data bus and the internal data bus and/or used states of the external data bus and the internal data bus. Therefore, a processing speed for the data can be improved as compared with the accessing at a fixed bus width.
The object is also achieved by the provision of a microcomputer, in which a central processing circuit, storing means, an internal data bus connecting the central processing circuit and the storing means and a transmission/reception buffer arranged between an external data bus and the internal data bus, comprising:
a ready flag for outputting a busy signal in cases where data is held in the transmission/reception buffer;
a timer for measuring an elapsed time starting from a time that the busy signal is output by the ready flag and outputting a time-out signal at a time that the elapsed time reaches a prescribed value; and
a logical circuit for outputting the busy signal output from the ready flag to an outside in a prescribed time-period extending from the outputting of the busy signal performed by the ready flag to the outputting of the time-out signal performed by the timer.
In the above configuration, in cases where an abnormal state occurs in a preceding data reception in the microcomputer after preceding data transmitted from the outside such as a host computer is held in the transmission/reception buffer, the preceding data is not read out to the central processing unit but is kept holding in the transmission/reception buffer. Also, in cases where an abnormal state occurs in a preceding data transmission in the microcomputer after preceding data to be transmitted to the outside such as a host computer is held in the transmission/reception buffer, the preceding data is not read out to the outside but is kept holding in the transmission/reception buffer. In this data holding state of the transmission/reception buffer, the ready flag outputs the busy signal to the logical circuit to output the busy signal from the logical circuit, so that a write-in of current data to the transmission/reception buffer is inhibited in a current data transmission/reception.
However, because an elapsed time is measured in the timer and because the busy signal is not output from the logical circuit after the prescribed time-period passes, the current data is written in and held in the transmission/reception buffer in the current data transmission/reception after the prescribed time-period passes.
Accordingly, even though a normal data reception cannot be performed in the transmission/reception buffer during the prescribed time-period, because the transmission/reception buffer is released from the inhibition of the current data reception and is returned to a normal state, the normal data reception can be performed in the transmission/reception buffer after the prescribed time-period passes, so that an operation reliability of the microcomputer can be improved.
The object is also achieved by the provision of a microcomputer, in which a central processing circuit, storing means, an internal data bus connecting the central processing circuit and the storing means and a transmission/reception buffer arranged between an external data bus and the internal data bus, comprising:
a latch signal producing circuit for receiving a referential clock signal used for a data transmission/reception and a write control signal indicating a write period from the external data bus and outputting a latch signal at an edge timing of the referential clock signal in the write period, wherein the transmission/reception buffer latches data from the external data bus according to the latch signal output from the latch signal producing circuit.
In the above configuration, because the transmission/reception buffer latches data from the external data bus according to the latch signal which is output at the edge timing of the referential clock signal in the write period, the transmission/reception buffer latches the data of the external data bus at the edge timing of the referential clock signal in the write period.
Accordingly, even though the data holding of the transmission/reception buffer at the edge timing of the write control signal is not guaranteed in the microcomputer, the data of the external data bus can be reliably latched and held in the transmission/reception buffer, so that an operation reliability of the microcomputer can be improved.
The object is also achieved by the provision of a microcomputer, in which a central processing circuit, storing means, an internal data bus connecting the central processing circuit and the storing means and a transmission/reception buffer arranged between an external data bus and the internal data bus, comprising:
an enciphering circuit, having a second transmission/reception buffer, for enciphering or deciphering data stored in the second transmission/reception buffer;
a selector, connected with the external data bus, for selecting either the transmission/reception buffer or the second transmission/reception buffer as an internal connected buffer to directly connect the external data bus and the internal connected buffer; and
a selector flag, in which a value is written by the central processing unit, for outputting a selector signal corresponding to the value to the selector to make the selector determine the internal connected buffer according to the selector signal.
In the above configuration, in cases where data transmitted from an outside such as a host computer to the microcomputer is enciphered, or in cases where it is required to encipher data to be transmitted from the microcomputer to the outside, the central processing unit writes a value in the selector flag, the selector flag outputs a selection signal corresponding to the value to the selector, and the selector selects the second transmission/reception buffer according to the selector signal to directly connect the external data bus and the second transmission/reception buffer. Therefore, enciphered data transmitted from the outside is stored in the second transmission/reception buffer through the external data bus and is deciphered in the enciphering unit, and the deciphered data is processed in the central processing unit. Also, data to be transmitted from the microcomputer is once stored in the second transmission/reception buffer and is enciphered in the enciphering unit, and the enciphered data is transmitted to the outside through the external data bus.
Accordingly, because a direct transmission/reception of data can be performed between the second transmission/reception buffer and the external data bus in cases where it is required to decipher or encipher the data, in comparison with a case that the data is once stored in the transmission/reception buffer and is transferred to the enciphering unit, a data processing time can be shortened by a data transferring time, so that an operation reliability of the microcomputer can be improved.